Name
Abstract | ||
|---|---|---|
We present v2c, a tool for translating Verilog to C. The tool accepts synthesizable Verilog as input and generates a word-level C program as an output, which we call the software netlist. The generated program is cycle-accurate and bit precise. The translation is based on the synthesis semantics of Verilog. There are several use cases for v2c, ranging from hardware property verification, co-verification to simulation and equivalence checking. This paper gives details of the translation and demonstrates the utility of the tool. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1007/978-3-662-49674-9_38 | TACAS |
Field | DocType | Volume |
Formal equivalence checking,Netlist,Programming language,Use case,Computer science,Semulation,Ranging,Software,Verilog,Semantics | Conference | 9636 |
ISSN | Citations | PageRank |
0302-9743 | 3 | 0.40 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajdeep Mukherjee | 1 | 11 | 3.40 |
| Michael Tautschnig | 2 | 425 | 25.84 |
| Daniel Kroening | 3 | 3084 | 187.60 |