Abstract | ||
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Recently, static random access memory (SRAM)based field programmable gate arrays (FPGAs) are used for various systems. Since such SRAM-based FPGAs are programmable, their use over a long period must accommodate the use of a partly damaged programmable gate array. However, since current FPGAs use a serial configuration line for their configuration and the serial configuration circuit is invariably first broken circuit. Therefore, currently available FPGAs cannot accommodate the use of a partly damaged programmable gate array. However, if a partly damaged programmable gate array could be used, then the lifetime of VLSIs would be increased drastically. To extend the lifetime of programmable devices, FPGA should use a parallel configuration architecture instead of the serial configuration architecture of currently available FPGAs. This paper therefore clarifies the benefits of the parallel configuration architecture on an optically reconfigurable gate array (ORGA) VLSI using the designs of an ORGA-VLSI and a currently available serial-configuration FPGA. |
Year | Venue | Field |
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2015 | 2015 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION (SII) | Computer architecture,Computer science,Programmable logic array,Field-programmable gate array,Static random-access memory,Control engineering,Gate array,Computer hardware,Very-large-scale integration,Reconfigurable computing,Macrocell array |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
3 | 1 |
Name | Order | Citations | PageRank |
---|---|---|---|
Minoru Watanabe | 1 | 137 | 43.46 |