Paper Info
Title
A 250uW 2.4GHz Fast-Lock Fractional-N Frequency Generation for Ultra-Low-Power Applications
Abstract
This paper presents a fast-lock 2.4GHz fractional-N phase-locked loop (PLL) for ultra-low-power applications. To minimize power consumed by all the other circuits except for the main oscillator, we propose a master-slave PLL structure where a low-frequency master PLL is followed by a slave injection-locked oscillator operating at high-frequency. A frequency-error compensation circuit is also implemented in the slave oscillator to eliminate possible drift in the free-running frequency. With a fractional-N coarse-lock unit in the master PLL and a fine frequency initialization unit in the slave oscillator, the PLL supports two fast-lock modes – 1) start-up locking from deep power down mode and 2) instantaneous relocking from standby mode. The implemented PLL in 65nm CMOS consumes 250μW from 0.8V supply, demonstrating a power efficiency of 0.102mW/GHz. The PLL performs the two fast-lock operations with lock times of less than 22μs from deep power down and 1μs from standby, respectively.
Year
DOI
Venue
2017
10.1109/TCSII.2016.2551598
IEEE Transactions Circuits and Systems II: Express Briefs
Keywords
Field
DocType
Clock generation,clock multiplier,fast-lock,frequency synthesizer,injection-locked PLL,master-slave,phase-locked loop (PLL),ultra-low-power
Electrical efficiency,Phase-locked loop,Standby power,Control theory,Crystal oscillator frequencies,PLL multibit,CMOS,Electronic engineering,Frequency synthesizer,Direct digital synthesizer,Mathematics
Journal
Volume
Issue
ISSN
PP
99
1549-7747
Citations 
PageRank 
References 
1
0.39
0
Authors
9
Name
Order
Citations
PageRank
Seunghwan Hong110.39
Shinwoong Kim211.74
Seungnam Choi3173.57
Hwasuk Cho423.12
Jaehyeong Hong510.39
Young Hun Seo610.39
Byungsub Kim716537.71
Hong-june Park846572.93
Jae-yoon Sim950883.58