Title
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays
Abstract
Capacitor matching influences linearity performance, which is a critical measure of analog-to-digital converters (ADCs). Various placement techniques have been proposed to eliminate both systematic and random mismatches of capacitor pairs. However, a placement technique that eliminates capacitor mismatches may not result in good linearity performance for successive-approximation-register (SAR) ADCs because their linearity performance is related to the accuracy of their binary-weighted continued ratio. This paper addresses the critical problem of placement estimation based on ratio mismatch M, overall correlation coefficient L, and performance metrics. A low M and a high L value do not imply higher linearity performance. Therefore, we propose a partition-centering-based symmetry placement algorithm for the layout considering parasitic capacitance matching. The experimental results show that the proposed placement approach can achieve higher linearity performance and a shorter placement generation time compared with the conventional approach.
Year
DOI
Venue
2017
10.1109/TCAD.2016.2561403
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
Field
DocType
Analog placement,binary-weighted continued ratio,capacitance ratio mismatch,spatial correlation coefficient,successive-approximation-register (SAR) ADC,unit capacitor array placement
Correlation coefficient,Capacitor,Capacitance,Parasitic capacitance,Linearity,Electronic engineering,Converters,Partition (number theory),Mathematics,Binary number
Journal
Volume
Issue
ISSN
36
1
0278-0070
Citations 
PageRank 
References 
1
0.38
16
Authors
3
Name
Order
Citations
PageRank
Chien-Chih Huang122410.26
Jwu-E Chen222328.37
Chin-Long Wey331656.51