Title
Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.
Abstract
A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 mu m opto-CMOS process fed at 3.3V and due to the highly effective integrated pin photodiode it operates at mu W. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0dBm and -25.5dBm are achieved, respectively, for lambda = 635nm and lambda = 675nm (BER = 10(-9)) with an energy efficiency of 2 pJ/bit.
Year
DOI
Venue
2016
10.3390/s16060761
SENSORS
Keywords
Field
DocType
integrated optoelectronics,integrated pin photodiode,integrating receiver
Sense amplifier,Electric power,Efficient energy use,Electronic engineering,Engineering,dBm,Megabit,Photodiode
Journal
Volume
Issue
ISSN
16
6
1424-8220
Citations 
PageRank 
References 
0
0.34
0
Authors
4
Name
Order
Citations
PageRank
Carlos Sánchez-Azqueta100.34
Bernhard Goll2156.08
Santiago Celma314543.45
Horst Zimmermann42915.60