Title | ||
---|---|---|
A 70.4 dB voltage gain, 2.3 dB NF, fully integrated multi-standard UHF receiver front-end in CMOS 130-nm. |
Abstract | ||
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The design of a fully integrated multi-standard UHF receiver front-end to be embedded in environmental data collection satellites is proposed. The circuit operates under the requirements of both SBCDA and the ARGOS 3. For that, the specifications of a multi-standard receiver front-end are firstly derived and then the implementation of a 70.4dB voltage gain, 2.3dB NF, 48mW energy consumption, single-ended input and differential quadrature output receiver front-end in 130-nm CMOS standard technology is presented. The design is validated through post-layout simulation. |
Year | DOI | Venue |
---|---|---|
2016 | 10.1016/j.mejo.2016.03.001 | Microelectronics Journal |
Keywords | Field | DocType |
ARGOS,SBCDA,UHF receiver,CMOS,LNA,Mixer,Quadrature | Radio receiver design,Voltage,Electronic engineering,CMOS,Engineering,Quadrature (mathematics),Electrical engineering,Ultra high frequency,Receiver front end,Energy consumption | Journal |
Volume | ISSN | Citations |
52 | 0026-2692 | 0 |
PageRank | References | Authors |
0.34 | 6 | 7 |
Name | Order | Citations | PageRank |
---|---|---|---|
Carlos A. M. Costa Júnior | 1 | 0 | 0.34 |
José B. Sales Filho | 2 | 0 | 0.34 |
g c l cunha | 3 | 1 | 1.06 |
Belfort, D. | 4 | 2 | 1.11 |
C. Catunda | 5 | 9 | 2.93 |
Robson Nunes de Lima | 6 | 3 | 4.19 |
v bourguet | 7 | 1 | 0.72 |