Name
Title | ||
|---|---|---|
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). |
Year | Venue | Field |
|---|---|---|
2016 | IACR Cryptology ePrint Archive | Hardware security module,Computer security,Computer science,Power noise,Computer hardware |
DocType | Volume | Citations |
Journal | 2016 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daisuke Fujimoto | 1 | 25 | 6.52 |
| Shivam Bhasin | 2 | 311 | 58.38 |
| Makoto Nagata | 3 | 285 | 76.47 |
| Jean-Luc Danger | 4 | 794 | 83.57 |