Title
A SVM Surrogate Model-Based Method for Parametric Yield Optimization.
Abstract
Yield optimization is a challenging topic in electronic circuit design. Methods for yield optimization based on Monte Carlo (MC) analysis of a circuit whose behavior is reproduced by simulations usually require too many time expensive simulations to be effective for iterative optimization. In this paper, we propose a method which tackles the yield optimization problem by combining a support vector machine (SVM) surrogate model (SM) of the circuit to perform the MC analysis and evaluate the yield, and an efficient optimization method to maximize the yield evaluated using the SVM SM. We report the numerical results obtained for the design of two real consumer circuits provided by STMicroelectronics, and we compare these results with the ones obtained using the industrial benchmark currently adopted at STMicroelectronics for yield optimization. These preliminary results show that the method is promising to be very efficient and capable of reaching design solutions with high values of the yield.
Year
DOI
Venue
2016
10.1109/TCAD.2015.2501307
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
Field
DocType
Optimization,Integrated circuit modeling,Analytical models,Support vector machines,Algorithm design and analysis,Computational modeling,Numerical models
Continuous optimization,Probabilistic-based design optimization,Mathematical optimization,Derivative-free optimization,Global optimization,Computer science,Discrete optimization,Meta-optimization,Test functions for optimization,Surrogate model
Journal
Volume
Issue
ISSN
35
7
0278-0070
Citations 
PageRank 
References 
5
0.46
7
Authors
3
Name
Order
Citations
PageRank
Angelo Ciccazzo1383.59
Gianni Di Pillo2706.55
Vittorio Latorre3315.16