Name
Title | ||
|---|---|---|
Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance. |
Abstract | ||
|---|---|---|
A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TCSII.2016.2530902 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Clamps,Delays,Rails,Latches,Logic gates,Low voltage,Layout | Logic gate,Current mirror,Dissipation,Efficient energy use,Voltage,Electronic engineering,Low voltage,Energy consumption,Mathematics,Power consumption | Journal |
Volume | Issue | ISSN |
63 | 7 | 1549-7747 |
Citations | PageRank | References |
2 | 0.41 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dawei Liu | 1 | 30 | 9.79 |
| Simon J. Hollis | 2 | 75 | 6.89 |
| Harry C. P. Dymond | 3 | 2 | 0.41 |
| Neville McNeill | 4 | 13 | 4.46 |
| Bernard H. Stark | 5 | 15 | 3.80 |