Name
Abstract | ||
|---|---|---|
A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator input-referred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1587/elex.13.20160115 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
stochastic flash ADC, comparator, mismatch, CMOS, genetic algorithm | Comparator,Computer science,CMOS,Electronic engineering,Flash ADC,Offset (computer science),Genetic algorithm | Journal |
Volume | Issue | ISSN |
13 | 6 | 1349-2543 |
Citations | PageRank | References |
2 | 0.45 | 7 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tetsuo Asano | 1 | 1448 | 229.35 |
| Yusaku Hirai | 2 | 7 | 2.38 |
| Sadahiro Tani | 3 | 9 | 4.51 |
| Shinya Yano | 4 | 5 | 0.93 |
| Ikkyun Jo | 5 | 9 | 3.39 |
| Toshimasa Matsuoka | 6 | 69 | 20.42 |