Name
Abstract | ||
|---|---|---|
The use of a multiple-input floating-gate transistor as the main element for effecting the correlation of two binary sequences is proposed and validated. A complete architecture is proposed to implement a correlating system. The algorithm is discussed and the implementation of a circuit for 256-bit sequences in 0.35 mu m CMOS technology is presented as a testing vehicle. Its use is furthermore proposed as a pilot baseband signal detector for a wireless communication system. The manufactured circuit offers favorable performance with a clock signal of up to 25MHz with a 2.3V supply voltage and 20mW of power consumption. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1587/elex.13.20151061 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
correlator, CMOS, floating-gate, pilot-signal detector | Computer science,Pseudorandom binary sequence,Electronic engineering,CMOS,Computer hardware | Journal |
Volume | Issue | ISSN |
13 | 3 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Agustín Santiago Medina-Vázquez | 1 | 5 | 3.76 |
| Marco Antonio Gurrola-Navarro | 2 | 6 | 4.80 |
| José M. Arce-Zavala | 3 | 0 | 0.34 |
| Maria Elena Meda-campaña | 4 | 9 | 3.31 |