Name
Title | ||
|---|---|---|
Nonlinear Pfd Free Of Glitches And Blind Zone For A Fast Locking Pll With Reduced Reference Spur |
Abstract | ||
|---|---|---|
A simple nonlinear PFD circuit designed to achieve reduced reference spur and faster acquisition process for a PLL is proposed in this paper. The proposed nonlinear PFD is found to offer higher gain, eliminate glitches at the output and reduce both dead zone and reset delay when compared with the operation of conventional linear PFD (CL-PFD) and conventional NL-PFD (CNL-PFD). The PLL acquisition time got reduced by 50% and 11.69% while the reference spur 45% and 38.6% with respect to the CL-PFD and CNL-PFD respectively. Reference spur of -72.2 dBc, lock time of 1.548 mu s, area of 0.2mm(2) and power dissipation of 6.2mW are obtained for the prototype PLL using Proposed NL-PFD designed with 180 nm CMOS process. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1587/elex.13.20160328 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
nonlinear PFD, PLL, reference spur, lock time, blind zone | Glitch,Phase-locked loop,Nonlinear system,Computer science,Spur,Electronic engineering,Lock time,Electrical engineering | Journal |
Volume | Issue | ISSN |
13 | 10 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abdul Majeed Kottampara Kuppalath | 1 | 0 | 0.34 |
| Binsu J. Kailath | 2 | 0 | 2.70 |