Paper Info
Title
Low power high performance FinFET standard cells based on mixed back biasing technology
Abstract
With the decrease in transistor feature size, power consumption, especially leakage power, has become a most important design concern. Because of their superior electrical properties and design flexibility, fin-type field-effect transistors (FinFETs) seem to be the most promising option in low-power applications. In order to support the VLSI digital system design flow based on logic synthesis, this paper proposes a design method for low-power high-performance standard cells based on IG-mode FinFETs. Such a method is derived on the basis of appropriately and artfully designing and optimizing the stacked structures in each standard cell, and applying the mixed forward and reverse back-gate bias technique in a well-chosen manner. The proposed method is also applicable when the supply voltage reduces to 0.5V to further reduce the leakage power consumption. By applying this design method, optimized IG-mode FinFET standard cells are generated, and they form a low-power high-performance standard cell library. Simulation results of the library cells indicate that the performance of the standard cells designed with the proposed method can be maintained while reducing leakage consumption by a factor of 58.9 at most. The 16-bit ripple carry adder implemented with this library can acquire up to 17.5% leakage power reduction. Copyright © 2016 The Institute of Electronics, Information and Communication Engineers.
Year
DOI
Venue
2016
10.1587/transele.E99.C.974
IEICE Transactions on Electronics
Keywords
Field
DocType
VLSI, FinFET, standard cell, stacking, back biasing
Electronic engineering,Standard cell,Engineering,Very-large-scale integration,Electrical engineering,Biasing,Stacking
Journal
Volume
Issue
ISSN
E99C
8
1745-1353
Citations 
PageRank 
References 
0
0.34
8
Authors
6
Name
Order
Citations
PageRank
Wang Tian11715.16
Xiaoxin Cui2356.59
Liao Kai352.09
Nan Liao4354.56
Cui Xiaole52115.35
Dunshan Yu64412.56