Name
Abstract | ||
|---|---|---|
This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor building block called 1P-2N and its complementary block 2P-1N. It is shown that all proposed latches have better soft error rate (SER) performance as compared to the SE-tolerant latches reported till date. It is also shown that the proposed con... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TC.2015.2509983 | IEEE Transactions on Computers |
Keywords | Field | DocType |
Latches,Circuit faults,Impedance,Transient analysis,Clocks,Feedback loop,Delays | Soft error,Dissipation,Computer science,Real-time computing,CMOS,Electrical impedance,Feedback loop,VHDL,Boolean expression,Clock rate | Journal |
Volume | Issue | ISSN |
65 | 9 | 0018-9340 |
Citations | PageRank | References |
2 | 0.40 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anjan Kumar Pudi N. S | 1 | 2 | 0.40 |
| Maryam Shojaei Baghini | 2 | 86 | 29.67 |