Name
Title | ||
|---|---|---|
Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching. |
Abstract | ||
|---|---|---|
The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective channel control and lower power consumption. However, the gate-misalignment problem resulting from process variation and the parasitic resistance resulting from interconnecting wires based on the FinFET technology becomes even more severe compared with the conventional planar CMOS technology. Such gate misalignment and unwanted parasitic resistance may increase the threshold voltage and decrease the drain current of transistors. When applying the FinFET technology to analog circuit design, the variation of drain currents can destroy current-ratio matching among transistors and degrade circuit performance. In this article, we present the first FinFET placement and routing algorithms for layout generation of a common-centroid FinFET array to precisely match the current ratios among transistors. Experimental results show that the proposed matching-driven FinFET placement and routing algorithms can obtain the best current-ratio matching compared with the state-of-the-art common-centroid placer. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2856031 | ACM Trans. Design Autom. Electr. Syst. |
Keywords | Field | DocType |
Analog placement,routing,FinFET,gate misalignment,parasitic resistance,common centroid,current-ratio matching | Parasitic element,Computer science,Parallel computing,Communication channel,CMOS,Electronic engineering,Planar,Process variation,Transistor,Threshold voltage,Centroid | Journal |
Volume | Issue | ISSN |
21 | 3 | 1084-4309 |
Citations | PageRank | References |
1 | 0.35 | 18 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Po-Hsun Wu | 1 | 52 | 6.05 |
| Mark Po-Hung Lin | 2 | 165 | 16.87 |
| Xin Li | 3 | 530 | 60.02 |
| Tsung-Yi Ho | 4 | 1061 | 95.20 |