Name
Title | ||
|---|---|---|
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. |
Abstract | ||
|---|---|---|
This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise ... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/JSSC.2016.2563780 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Capacitors,Clocks,Routing,Capacitance,Generators,Signal to noise ratio,Redundancy | Asynchronous communication,Clock generator,Comparator,Settling time,Computer science,Signal-to-noise ratio,Electronic engineering,Effective number of bits,CMOS,Successive approximation ADC,Electrical engineering | Journal |
Volume | Issue | ISSN |
51 | 8 | 0018-9200 |
Citations | PageRank | References |
6 | 0.56 | 8 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wan Kim | 1 | 50 | 4.96 |
| Hyeok-Ki Hong | 2 | 64 | 8.23 |
| Yi-Ju Roh | 3 | 11 | 1.82 |
| Hyun-Wook Kang | 4 | 65 | 7.86 |
| Sun-Il Hwang | 5 | 17 | 3.28 |
| Dong-Shin Jo | 6 | 46 | 5.31 |
| Dong-Jin Chang | 7 | 20 | 3.20 |
| Min-Jae Seo | 8 | 23 | 4.08 |
| Seung-Tak Ryu | 9 | 299 | 46.61 |