Name
Abstract | ||
|---|---|---|
Hybrid main memory with both DRAM and emerging non-volatile memory (NVM) becomes a promising solution for high performance and energy-efficient embedded systems. Cache plays an important role and highly affects the number of write backs to NVM and DRAM blocks. However, existing cache policies fail to fully address the significant asymmetry between NVM operations (especially writes) and DRAM operations, leading to non-optimal system designs. We propose a write-back aware last-level cache management scheme for the hybrid main memory, which improves the cache hit ratio of NVM memory blocks and minimizes write-backs to NVM. Experimental results show that our proposed framework leads to better performance and energy saving compared with the state-of-the-art cache management scheme for hybrid main memory architecture. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2897937.2898110 | DAC |
Field | DocType | Citations |
Interleaved memory,Cache pollution,CPU cache,Computer science,Cache,Cache-only memory architecture,Page cache,Real-time computing,Cache coloring,Non-uniform memory access | Conference | 7 |
PageRank | References | Authors |
0.42 | 10 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Deshan Zhang | 1 | 8 | 0.76 |
| Lei Ju | 2 | 265 | 29.03 |
| Mengying Zhao | 3 | 81 | 8.31 |
| Xiang Gao | 4 | 55 | 6.33 |
| zhiping jia | 5 | 463 | 60.64 |