Name
Title | ||
|---|---|---|
Clear: <u>c</u>ross-<u>l</u>ayer <u>e</u>xploration for <u>a</u>rchitecting <u>r</u>esilience combining hardware and software techniques to tolerate soft errors in processor cores. |
Year | Venue | DocType |
|---|---|---|
2016 | DAC | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
11 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eric Cheng | 1 | 16 | 2.97 |
| Shahrzad Mirkhani | 2 | 127 | 9.56 |
| Lukasz G. Szafaryn | 3 | 141 | 7.69 |
| Chen-Yong Cher | 4 | 770 | 39.92 |
| Hyungmin Cho | 5 | 413 | 22.09 |
| Kevin Skadron | 6 | 6188 | 384.18 |
| Mircea Stan | 7 | 85 | 7.09 |
| klas lilja | 8 | 13 | 2.02 |
| Jacob A. Abraham | 9 | 6 | 1.72 |
| Pradip Bose | 10 | 2790 | 210.58 |
| Subhasish Mitra | 11 | 3657 | 228.90 |