Abstract | ||
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The high amount of memory requests from massive threads may easily cause cache contention and cache-miss-related resource congestion on GPUs. This paper proposes a simple yet effective performance model to estimate the impact of cache contention and resource congestion as a function of the number of warps/thread blocks (TBs) to bypass the cache. Then we design a hardware-based dynamic warp/thread-block level GPU cache bypassing scheme, which achieves 1.68x speedup on average on a set of memory-intensive benchmarks over the baseline. Compared to prior works, our scheme achieves 21.6% performance improvement over SWL-best [29] and 11.9% over CBWT-best [4] on average. |
Year | DOI | Venue |
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2016 | 10.1145/2897937.2897966 | DAC |
Keywords | Field | DocType |
model-driven approach,warp/thread-block level GPU cache bypassing,memory requests,cache contention,cache-miss-related resource congestion,memory-intensive benchmarks | Cache-oblivious algorithm,Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Page cache,Cache coloring,Smart Cache,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4673-8730-9 | 6 | 0.40 |
References | Authors | |
26 | 6 |
Name | Order | Citations | PageRank |
---|---|---|---|
Hongwen Dai | 1 | 28 | 3.14 |
Chao Li | 2 | 132 | 6.04 |
Huiyang Zhou | 3 | 994 | 63.26 |
Saurabh Gupta | 4 | 218 | 11.61 |
Christos Kartsaklis | 5 | 26 | 4.82 |
Mike Mantor | 6 | 167 | 9.22 |