Name
Title | ||
|---|---|---|
0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASICON.2011.6157278 | ASICON |
Keywords | Field | DocType |
logic gates,phase locked loops,digital control,low voltage,solids,logic gate,cmos integrated circuits,oscillators,robust control,digitally controlled oscillator,high frequency,cmos technology,tuning | Phase-locked loop,Digitally controlled oscillator,Logic gate,Computer science,Electronic engineering,CMOS,Low voltage,Jitter,Electrical engineering,Digital control,Effective frequency | Conference |
Citations | PageRank | References |
1 | 0.38 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chia-Wen Chang | 1 | 181 | 16.85 |
| Shyh-Jye Jou | 2 | 420 | 275.67 |
| Yuan-Hua Chu | 3 | 20 | 2.20 |