Name
Abstract | ||
|---|---|---|
New architectures for extreme-scale computing need to be designed for higher energy efficiency than current systems. One recently-proposed extreme-scale many core radically simplifies the architecture, and proposes a cluster-based on-chip memory hierarchy without hardware cache coherence. To program for such an environment, this paper proposes two approaches. They use shared-memory programming either inside clusters only, or both inside and across clusters. Both approaches rely on ISA support for writeback and self-invalidation operations. Our simulation results show that hardware-incoherent cache hierarchies with our support deliver reasonable performance for applications that were not written for such hierarchies. Specifically, for execution within a cluster, the average execution time of the applications is 2% higher than with hardware cache coherence, for execution across multiple clusters, it is 5% higher than with hardware cache coherence. This is accomplished with minimal hardware support. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/IPDPS.2016.76 | 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS) |
Keywords | Field | DocType |
Cache coherence,Hardware-incoherent caches,Software-managed caches | Cache invalidation,Computer science,Cache,MESI protocol,Page cache,Cache coloring,Computer hardware,Distributed computing,Computer architecture,Cache-oblivious algorithm,Cache pollution,Parallel computing,Cache algorithms | Conference |
ISSN | ISBN | Citations |
1530-2075 | 978-1-5090-2141-3 | 1 |
PageRank | References | Authors |
0.35 | 17 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wooil Kim | 1 | 120 | 16.95 |
| Sanket Tavarageri | 2 | 57 | 4.41 |
| P. Sadayappan | 3 | 4821 | 344.32 |
| Josep Torrellas | 4 | 3838 | 262.89 |