Paper Info
Title
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric.
Abstract
FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devices in environments with tight cost and power constraints. This is the case for datacenter servers, where a modestly-sized FPGA cannot accommodate the large number of diverse accelerators that datacenter applications need. This paper introduces DRAF, an architecture for bit-level reconfigurable logic that uses DRAM subarrays to implement dense lookup tables. DRAF overlaps DRAM operations like bitline precharge and charge restoration with routing within the reconfigurable routing fabric to minimize the impact of DRAM latency. It also supports multiple configuration contexts that can be used to quickly switch between different accelerators with minimal latency. Overall, DRAF trades off some of the performance of FPGAs for significant gains in area and power. DRAF improves area density by 10x over FPGAs and power consumption by more than 3x, enabling DRAF to satisfy demanding applications within strict power and cost constraints. While accelerators mapped to DRAF are 2-3x slower than those in FPGAs, they still deliver a 13x speedup and an 11x reduction in power consumption over a Xeon core for a wide range of datacenter tasks, including analytics and interactive services like speech recognition.
Year
DOI
Venue
2017
10.1109/MM.2017.50
IEEE Micro
Keywords
DocType
Volume
Random access memory,Field programmable gate arrays,Context modeling,DRAM chips,Acceleration,Digital signal processing,Arrays
Journal
37
Issue
ISSN
Citations 
3
0272-1732
3
PageRank 
References 
Authors
0.39
33
7
Name
Order
Citations
PageRank
Mingyu Gao12699.85
Christina Delimitrou244420.12
Dimin Niu360931.36
Krishna T. Malladi424918.37
Hongzhong Zheng51225.94
Bob Brennan6601.93
Christos Kozyrakis75817355.99