Paper Info
Title
Model driven design of heterogeneous synchronous embedded systems.
Abstract
Synchronous embedded systems are becoming more and more complicated and are usually implemented with integrated hardware/software solutions. This implementation manner brings new challenges to the traditional model-driven design environments such as SCADE and STATEMATE, that supports pure hardware or software design. In this paper, we propose a co-design tool Tsmart-Edola to facilitate the system developers, and automatically generate the executable VHDL code and C code from the for- mal verified SyncBlock computation model. SyncBlock is a lightweight high-level system specification model with well defined syntax, simulation and formal semantics. Based on which, the graphical model editor, graphical simulator, verification translator, and code generator are implemented and seamlessly integrated into the Tsmart-Edola. For evaluation, we apply Tsmart-Edola to the design of a real-world train controller based on the international standard IEC 61375. Several critical ambiguousness or bugs in the standard are detected during formal verification of the constructed system model. Furthermore, the generated VHDL code and C code of Tsmart-Edola outperform that of the state-of-the-art tools in terms of synthesized gate array resource consumption and binary code size.
Year
DOI
Venue
2016
10.1145/2970276.2970280
ASE
Keywords
Field
DocType
model driven development, computation model, hardware-software co-design
Static program analysis,Programming language,Software design,Computer science,Theoretical computer science,Code generation,Formal specification,VHDL,Formal methods,Executable,Formal verification,Embedded system
Conference
ISSN
ISBN
Citations 
1527-1366
978-1-5090-5571-5
2
PageRank 
References 
Authors
0.39
7
6
Name
Order
Citations
PageRank
Huafeng Zhang1324.52
Yu Jiang234656.49
Han Liu3444.34
Hehua Zhang410912.65
gu ming561.82
Jia-guang Sun61807134.30