Paper Info
Title
A Realization of Index Generation Functions Using Multiple IGUs
Abstract
This paper presents a method to realize index generation functions using multiple Index Generation Units (IGUs). The architecture implements index generation functions more efficiently than a single IGU when the number of registered vectors is very large. This paper also proves that independent linear transformations are necessary in IGUs for efficient realization. Experimental results confirm this statement.
Year
DOI
Venue
2016
10.1109/ISMVL.2016.17
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)
Keywords
Field
DocType
Random function,CAM,content-addressable memory,linear decomposition,linear transformation,statistical analysis
Computer-aided manufacturing,Architecture,Content-addressable memory,Computer science,Electronic engineering,Memory management,Linear map,Multiplexing,Linear circuit,Random function
Conference
ISSN
ISBN
Citations 
0195-623X
978-1-4673-9490-1
3
PageRank 
References 
Authors
0.44
10
1
Name
Order
Citations
PageRank
Tsutomu Sasao11083141.62