Title
Design of Ratioless Ternary Inverter Using Graphene Barristor.
Abstract
This study proposes a design of a ternary logic inverter using graphene barristor (GB). To design a multiplevalued logic gate, controlling threshold voltages of the unit device should be easy. We determined that the doping concentration of the graphene can easily control the operation voltage of the GB. To realize an ideal ternary logic gate, the concept of a single pole triple throw switch is proposed and designed using the GB. The designed ratioless GB ternary inverter was simulated using SPICE and Mathematica. Voltage transfer characteristics of the proposed ternary invertershowed sharp ternary characteristics and its static power consumption was nearly zero.
Year
Venue
Field
2016
ISMVL
Inverter,Logic gate,Spice,Computer science,Voltage,Electronic engineering,Ternary operation,Resistor,Schottky diode,Threshold voltage,Electrical engineering
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
3
6
Name
Order
Citations
PageRank
Sunwoo Heo100.68
Jinwoo Noh200.34
Yun Ji Kim300.34
Soyoung Kim416822.15
Abdul Karim Khan500.34
Byoung Hun Lee6324.71