Name
Abstract | ||
|---|---|---|
A fully integrated digitally controlled oscillator (DCO) used as an on-chip clock is presented in this paper. The DCO system is implemented using symmetrical NAND based digitally controlled delay line (DCDL) structure which has balanced loading with balanced number of fan-in and fan-out. This unique configuration maintains delay linearity, also the frequency tuning is easily accomplished without any external controller structures which makes it less sensitive to process variation. Using a 65 nm CMOS process and 1.2 V supply voltage, the proposed DCO has a frequency range of (14–203) MHz occupies an on-chip area of about 0.0015 μm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
and power dissipation of 0.58 mW @ 203 MHz frequency. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ICICDT.2016.7542041 | 2016 International Conference on IC Design and Technology (ICICDT) |
Keywords | Field | DocType |
on-chip integration,fully integrated digitally controlled oscillator,DCO system,on-chip clock,DCDL structure,symmetrical NAND based digitally controlled delay line,balanced loading,balanced number,fan-in,fan-out,delay linearity,frequency tuning,CMOS process,size 65 nm,voltage 1.2 V,frequency 14 MHz to 203 MHz,power 0.58 mW | Digitally controlled oscillator,Control theory,Dissipation,Voltage,Linearity,Electronic engineering,NAND gate,CMOS,Process variation,Engineering | Conference |
ISBN | Citations | PageRank |
978-1-5090-0321-1 | 0 | 0.34 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shanthi Sudalaiyandi | 1 | 9 | 3.04 |
| Gilles Masson | 2 | 20 | 2.18 |
| Mykhailo Zarudniev | 3 | 0 | 0.68 |