Name
Abstract | ||
|---|---|---|
This paper proposes a two-stage transistor routing approach that synergizes the merits of channel routing and integer linear programming for CMOS standard cells. It can route 185 cells in 611 seconds. About 21% of cells obtained by our approach have smaller wire length than their handcrafted counterparts. Only 11% of cells use more vias than their handcrafted counterparts. Our router completes routing of many cells that cannot be routed by an industrial one. |
Year | Venue | Keywords |
|---|---|---|
2016 | 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) | Routing,standard cell,transistor,integer linear programming |
Field | DocType | ISSN |
Computer science,Parallel computing,Communication channel,CMOS,Integer programming,Standard cell,Routing (electronic design automation),Router,Transistor | Conference | 1530-1591 |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsueh-Ju Lu | 1 | 1 | 0.81 |
| En-Jang Jang | 2 | 1 | 0.81 |
| Ang Lu | 3 | 1 | 0.81 |
| Yu Ting Zhang | 4 | 0 | 0.34 |
| Yu-He Chang | 5 | 0 | 0.34 |
| Chi-Hung Lin | 6 | 217 | 34.67 |
| Rung-Bin Lin | 7 | 173 | 28.42 |