Name
Abstract | ||
|---|---|---|
Generation of accurate IP power models requires determination of correct simulation conditions for the different input pins of the IP. Determining such a set of inputs for individual IP blocks in a design is expensive in cost and time, and is also highly error prone. Additionally, it is desirable to identify IP instances in a design, where these simulation conditions are not met. These are relevant problems in the context of modern day microprocessor designs, which are designed using a very large number of IPs, either developed in-house or sourced from external vendors. In this paper, we examine these problems in an industrial context and introduce FVCAG, a framework for enabling efficient and accurate power modelling. FVCAG enables a more thorough IP power modelling than that can be accomplished using current state of the art techniques. Experimental evaluation of the proposed framework on the standard cell library and macros used in the design of an industry class high performance microprocessor design demonstrates the accuracy and efficiency of proposed framework. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2934583.2934633 | ISLPED |
Keywords | Field | DocType |
Power modelling, power abstraction, IP characterization, formal verification, simulation, microprocessor design | Computer science,Microprocessor,Electronic engineering,Real-time computing,Large numbers,Standard cell,Microprocessor design,Macro,Embedded system,Formal verification | Conference |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arun Joseph | 1 | 4 | 3.48 |
| Spandana Rachamalla | 2 | 0 | 1.35 |
| Rahul M. Rao | 3 | 195 | 19.01 |
| Anand Haridass | 4 | 2 | 1.42 |
| Pradeep Kumar Nalla | 5 | 2 | 2.10 |