Name
Abstract | ||
|---|---|---|
Despite 20+ years of research on processor verification, it remains hard to use formal verification techniques in commercial processor development. There are two significant factors: scaling issues and return on investment. The scaling issues include the size of modern processor specifications, the size/complexity of processor designs, the size of design/verification teams and the (non)availability of enough formal verification experts. The return on investment issues include the need to start catching bugs early in development, the need to continue catching bugs throughout development, and the need to be able to reuse verification IP, tools and techniques across a wide range of design styles. |
Year | Venue | Field |
|---|---|---|
2016 | CAV | Software engineering,Return on investment,Computer science,Reuse,Intelligent verification,End-to-end principle,Register file,Design styles,Theoretical computer science,Formal verification |
DocType | Citations | PageRank |
Conference | 6 | 0.43 |
References | Authors | |
14 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alastair Reid | 1 | 13 | 1.78 |
| Rick Chen | 2 | 6 | 0.76 |
| Anastasios Deligiannis | 3 | 21 | 3.05 |
| David Gilday | 4 | 6 | 0.43 |
| David Hoyes | 5 | 6 | 0.43 |
| Will Keen | 6 | 6 | 0.43 |
| Ashan Pathirane | 7 | 6 | 0.43 |
| Owen Shepherd | 8 | 6 | 0.43 |
| Peter Vrabel | 9 | 6 | 0.43 |
| Ali Zaidi | 10 | 6 | 0.43 |