Name
Abstract | ||
|---|---|---|
Non-standardized scan interface within and across system-on-chips (SoCs) limits test-data reuse for intellectual properties (IPs). To overcome this limitation, we present a flexible and dynamic scan interface architecture that enables reuse of test-data for a given IP across SoCs with different scan pin configurations. The dynamic nature of this architecture also enables variable shift frequencies across different IPs in a given SoC. The architecture decouples the scan pin requirements from the design cycle of the IPs. It also uses bidirectional scan pins to further reduce test cost by using as few as two pins. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/VTS.2016.7477308 | 2016 IEEE 34th VLSI Test Symposium (VTS) |
Keywords | Field | DocType |
flexible scan interface architecture,complex SoC,system-on-chips,intellectual properties,scan pin configurations,variable shift frequencies | Boundary scan,Dynamic Scan,Architecture,Computer science,Reuse,Electronic engineering,Bandwidth (signal processing),Computer hardware,Embedded system,Design cycle | Conference |
ISSN | Citations | PageRank |
1093-0167 | 2 | 0.58 |
References | Authors | |
15 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Milind Sonawane | 1 | 8 | 2.09 |
| Sailendra Chadalavada | 2 | 2 | 0.92 |
| Shantanu Sarangi | 3 | 2 | 1.59 |
| Amit Sanghani | 4 | 22 | 2.56 |
| Mahmut Yilmaz | 5 | 189 | 13.84 |
| Pavan Kumar Datla Jagannadha | 6 | 2 | 1.25 |
| Jonathon E. Colburn | 7 | 14 | 2.63 |