Name
Title | ||
|---|---|---|
Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications. |
Abstract | ||
|---|---|---|
A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 mu m Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture's circuit is 0.1 mW when the DLL is operated at 2 GHz. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.3390/s16101593 | SENSORS |
Keywords | Field | DocType |
delay step,delay range,time jitter,Delay-Locked Loop (DLL),charge pump,Capacitor-Reset Circuit (CRC) | Voltage,Delay-locked loop,Electronic engineering,CMOS,Picosecond,Jitter,Engineering,Charge pump,Semiconductor,Power consumption | Journal |
Volume | Issue | ISSN |
16 | 10.0 | 1424-8220 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bilal I Abdulrazzaq | 1 | 0 | 0.34 |
| Omar J Ibrahim | 2 | 0 | 0.34 |
| Shoji Kawahito | 3 | 270 | 67.13 |
| Roslina Sidek | 4 | 12 | 2.24 |
| Suhaidi Shafie | 5 | 21 | 7.17 |
| Nurul Amziah Md Yunus | 6 | 0 | 1.01 |
| Lini Lee | 7 | 0 | 1.69 |
| Izhal Abdul Halin | 8 | 9 | 2.87 |