Paper Info
Title
Garbling Gadgets for Boolean and Arithmetic Circuits.
Abstract
We present simple, practical, and powerful new techniques for garbled circuits. These techniques result in significant concrete and asymptotic improvements over the state of the art, for several natural kinds of computations. For arithmetic circuits over the integers, our construction results in garbled circuits with free addition, weighted threshold gates with cost independent of fan-in, and exponentiation by a fixed exponent with cost independent of the exponent. For boolean circuits, our construction gives an exponential improvement over the state of the art for threshold gates (including AND/OR gates) of high fan-in. Our construction can be efficiently instantiated with practical symmetric-key primitives (e.g., AES), and is proven secure under similar assumptions to that of the Free-XOR garbling scheme (Kolesnikov & Schneider, ICALP 2008). We give an extensive comparison between our scheme and state-of-the-art garbling schemes applied to boolean circuits.
Year
DOI
Venue
2016
10.1145/2976749.2978410
IACR Cryptology ePrint Archive
DocType
Volume
Citations 
Conference
2016
10
PageRank 
References 
Authors
0.48
18
3
Name
Order
Citations
PageRank
Marshall Ball1448.81
Tal G. Malkin22633152.56
Mike Rosulek333425.32