Name
Abstract | ||
|---|---|---|
This paper presents a phase-error cancellation (PEC) technique that can be employed to achieve fast lock in analogue phase-locked loops (PLLs). The PLL works in fast-lock mode during phase and frequency tracking, and is switched to normal mode after it is almost locked. Unstable system topology is introduced in this system for fast locking. This PEC technique is proposed to cancel the phase error ... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1049/iet-cds.2015.0201 | IET Circuits, Devices & Systems |
Keywords | Field | DocType |
analogue circuits,circuit stability,CMOS analogue integrated circuits,phase locked loops | System topology,Phase-locked loop,Oscillation,Phase error,Lock (computer science),Settling time,Control theory,Cmos process,Electronic engineering,Normal mode,Mathematics | Journal |
Volume | Issue | ISSN |
10 | 5 | 1751-858X |
Citations | PageRank | References |
0 | 0.34 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhaoming Ding | 1 | 7 | 2.80 |
| Haiqi Liu | 2 | 0 | 0.34 |
| Qiang Li | 3 | 81 | 21.66 |