Name
Abstract | ||
|---|---|---|
A 10-b ultralow-power successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a standard 0.18- μm CMOS technology is described. The architecture consists of a coarse and a fine SAR ADC. The 2-b coarse SAR presets the two MSB capacitive arrays of the fine SAR, thus avoiding the largest sources of dynamic power consumption. The use of two low-resolution comparators i... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TCSII.2016.2538139 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Switches,Capacitors,Latches,Capacitance,Low-power electronics,Power demand,Clocks | Preamplifier,Comparator,Effective number of bits,CMOS,Electronic engineering,Figure of merit,Dynamic demand,Successive approximation ADC,Mathematics,Low-power electronics | Journal |
Volume | Issue | ISSN |
63 | 10 | 1549-7747 |
Citations | PageRank | References |
2 | 0.39 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yulin Zhang | 1 | 52 | 12.72 |
| Edoardo Bonizzoni | 2 | 162 | 47.30 |
| Franco Maloberti | 3 | 686 | 144.70 |