Name
Abstract | ||
|---|---|---|
In this work, we present a family of architectures for polar decoders using a reduced-complexity successive-cancellation decoding algorithm that employs unrolling to achieve extremely high throughput values while retaining moderate implementation complexity. The resulting fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput in excess of 1 Tbps on a 65 nm ASIC at... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/TCSI.2016.2586218 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Throughput,Hardware,Computer architecture,Encoding,Systematics,Maximum likelihood decoding | Orders of magnitude (numbers),Efficient energy use,Computer science,Electronic engineering,Application-specific integrated circuit,Polar,Soft-decision decoder,Polar code,Decoding methods,Throughput | Journal |
Volume | Issue | ISSN |
63 | 9 | 1549-8328 |
Citations | PageRank | References |
4 | 0.43 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pascal Giard | 1 | 244 | 17.57 |
| Gabi Sarkis | 2 | 253 | 17.23 |
| Claude Thibeault | 3 | 107 | 14.35 |
| Warren J. Gross | 4 | 1106 | 113.38 |