Name
Abstract | ||
|---|---|---|
Nowadays, inter-task interferences are the main difficulty in analyzing the timing behavior of multicores. The timing predictable embedded multicore architecture MERASA, which allows safe worst-case execution time (WCET) estimations, has emerged as an attractive solution. In the architecture, WCET can be estimated by the upper bound delay (UBD) which can be bounded by the interference-aware bus arbiter (IABA) and the dynamic cache partitioning such as columnization or bankization. However, this architecture faces a dilemma between decreasing UBD and efficient shared cache utilization. To obtain tighter WCET estimation, we propose a novel approach that reduces UBD by optimizing bank-to-core mapping on the multicore system with IABA and the two-level partitioned cache. For this, we first present a new UBD computation model based on the analysis of inter-task interference delay, and then put forward the core-sequence optimization method of bank-to-core mapping and the optimizing algorithms with the minimum UBD. Experimental results demonstrate that our approach can reduce WCET from 4% to 37%. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1007/s11390-016-1691-x | J. Comput. Sci. Technol. |
Keywords | Field | DocType |
multicore, hard real-time task, bank-to-core mapping, upper bound delay optimization | Arbiter,Shared memory,Upper and lower bounds,Cache,Computer science,Parallel computing,Real-time computing,Interference (wave propagation),Multi-core processor,Bounded function,Computation,Distributed computing | Journal |
Volume | Issue | ISSN |
31 | 6 | 1860-4749 |
Citations | PageRank | References |
0 | 0.34 | 22 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jizan Zhang | 1 | 0 | 2.37 |
| Zhimin Gu | 2 | 111 | 14.40 |
| Ming-quan Zhang | 3 | 5 | 4.29 |