Name
Abstract | ||
|---|---|---|
A low-voltage high-PSRR CMOS voltage reference operating with picowatt power consumption is presented. The voltage reference is generated from the threshold voltage (VT) difference of two transistors biased in weak inversion. The VT difference is achieved through its dependence with the transistor dimensions. The high-PSRR is obtained using zero-VT transistors as active loads. The final circuit was designed in a 130 nm CMOS process and occupies around 0.0007 mm2 of silicon area while consuming just 18.5 pW at 27°C. Post-layout simulations present a 62 mV reference voltage with a temperature coefficient of 15 ppm/°C, for a temperature range from -25 to 125 °C and a Power Supply Rejection Ratio (PSRR) of -68.7 dB at 0.3 V of supply voltage.
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Year | DOI | Venue |
|---|---|---|
2016 | 10.5555/3145862.3145871 | SBCCI '16: 29th Symposium on Integrated Circuits and Systems Design
Belo Horizonte
Brazil
August, 2016 |
Keywords | DocType | ISBN |
Low-voltage, low-power, voltage reference, zero-V-T Transistor | Conference | 978-1-5090-2736-1 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Cordova | 1 | 0 | 0.34 |
| Arthur C. de Oliveira | 2 | 0 | 0.34 |
| Pedro Toledo | 3 | 0 | 0.34 |
| hamilton klimach | 4 | 71 | 20.07 |
| sergio bampi | 5 | 496 | 102.12 |
| Eric E. Fabris | 6 | 19 | 11.33 |