Name
Abstract | ||
|---|---|---|
Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However, overclocking, and error detection and correction capabilities of the double sampling methods are limited due to the fixed speculation window which lacks adaptability for tracking variations such as temperature. In this paper, we introduce a dynamic speculation window to be used in double sampling schemes for timing error detection and correction in pipelined logic paths. The proposed method employs online slack measurement and conventional shadow flipflop approach to adaptively overclock or underclock the design and also to detect and correct timing errors due to temperature and other variability effects. We demonstrate this method in the Xilinx Virtex VC707 FPGA for various benchmarks. We achieve a maximum of 71% overclocking with a limited area overhead of 1.9% LUTs and 1.7% flip-flops. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISVLSI.2016.13 | 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | Field | DocType |
Dynamic Speculation window,Adaptive Overclocking,Error detection and correction | Logic gate,Overclocking,Efficient energy use,Computer science,Field-programmable gate array,Algorithm,Real-time computing,Error detection and correction,Sampling (statistics),Virtex,Clock rate | Conference |
ISSN | ISBN | Citations |
2159-3469 | 978-1-4673-9040-8 | 3 |
PageRank | References | Authors |
0.39 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| rengarajan ragavan | 1 | 5 | 1.09 |
| Cedric Killian | 2 | 14 | 5.04 |
| Olivier Sentieys | 3 | 597 | 73.35 |