Paper Info
Title
Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements.
Abstract
With drastic device shrinking, low operating voltages, increasing complexities, and high speed operations, radiation-induced soft errors have posed an ever increasing reliability challenge to both combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise efficient soft error rate (SER) estimation methods, in order to evaluate the soft error vulnerabilities for cost-effective robust circuit design. Previous works either analyze only SER in combinational circuits or evaluate soft error vulnerabilities in sequential elements. In this paper, a joint SER estimation framework is proposed, which considers single-event transients (SETs) in combinational logic and multiple cell upsets (MCUs) in sequential components. Various masking effects are considered in the combinational SER estimation process, and several typical radiation-hardened and non-hardened flip-flop structures are analyzed and compared as the sequential elements. A schematic and layout co-simulation approach is proposed to model the MCUs for redundant sequential storage structures. Experimental results of a variety of ISCAS benchmark circuits using the Nangate 45nm CMOS standard cell library demonstrate the difference in soft error resilience among designs using different sequential elements and the importance of modeling MCUs in redundant structures.
Year
DOI
Venue
2016
10.1109/ISVLSI.2016.28
IEEE Computer Society Annual Symposium on VLSI
Keywords
Field
DocType
Soft error,hardened flip-flop,single-event upset,multiple cell upset
Logic gate,Sequential logic,Soft error,Circuit design,Combinational logic,Electronic engineering,Schematic,Standard cell,Engineering,Single event upset,Computer engineering
Conference
ISSN
Citations 
PageRank 
2159-3469
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
Ji Li19710.87
Jeff Draper229826.31