Paper Info
Title
IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing
Abstract
Hardware caches are widely employed in GPGPUs to achieve higher performance and energy efficiency. Incorporating hardware caches in GPGPUs, however, does not immediately guarantee enhanced performance and energy efficiency due to high cache contention and thrashing. To address the inefficiency of GPGPU caches, various adaptive techniques (e.g., warp limiting) have been proposed. However, relatively little work has been done in the context of creating an architectural framework that tightly integrates adaptive cache management techniques and investigating their effectiveness and interaction. To bridge this gap, we propose IACM, integrated adaptive cache management for high-performance and energy-efficient GPGPU computing. IACM integrates the state-of-the-art adaptive cache management techniques (i.e., cache indexing, bypassing, and warp limiting) in a unified architectural framework. Our quantitative evaluation demonstrates that IACM significantly improves the performance and energy efficiency of various GPGPU workloads over the baseline architecture (i.e., 98.1% and 61.9% on average).
Year
DOI
Venue
2016
10.1109/ICCD.2016.7753308
2016 IEEE 34th International Conference on Computer Design (ICCD)
Keywords
Field
DocType
IACM,integrated adaptive cache management,high-performance GPGPU computing,energy-efficient GPGPU computing,hardware caches,cache contention,cache thrashing,architectural framework,unified architectural framework
Cache,Instruction set,Computer science,Real-time computing,Benchmark (computing),Computer architecture,Efficient energy use,Parallel computing,Architecture framework,Cache algorithms,Thrashing,General-purpose computing on graphics processing units,Embedded system
Conference
ISSN
ISBN
Citations 
1063-6404
978-1-5090-5143-4
3
PageRank 
References 
Authors
0.38
13
3
Name
Order
Citations
PageRank
kyu yeun kim1102.22
Jinsu Park2367.43
Woongki Baek340225.85