Name
Abstract | ||
|---|---|---|
Recent propositions of diverse In-Memory Computing platforms have shown a promising alternative to classical Von Neumann computing models. Significant benefits, in terms of energy-efficiency and performance, are reported for in-memory arithmetic circuits, neural networks, CAM, cache hierarchy and even fully programmable processors. In contrast, design automation tools supporting the development of such designs are still in a nascent phase. By leveraging the native stateful logic operation capability of ReRAM devices, several logic synthesis flows have been reported. In this paper, we complement these flows with a detailed study on the technology mapping phase for ReRAM devices. We provide a delay-optimal solution for technology mapping without area constraint and propose further heuristics to achieve device count reduction and to support delay optimization under the constraint of parallel instruction dispatch. We report at least 3x less delay compared to the naïve technology mapping adopted in recent studies. The proposed heuristics achieve 56% on average reduction in device count. Finally, a range of performance trade-offs is identified by applying the constraint of parallel instruction dispatch without noticeable degradation of delay. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2966986.2967020 | ICCAD |
Keywords | Field | DocType |
Resistive RAM,In-memory computing,Dispatch parallelism | Logic synthesis,Computer science,In-Memory Processing,Electronic engineering,Real-time computing,Electronic design automation,Heuristics,Stateful firewall,Artificial neural network,Von Neumann architecture,Resistive random-access memory | Conference |
ISSN | Citations | PageRank |
1933-7760 | 3 | 0.42 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Debjyoti Bhattacharjee | 1 | 26 | 9.84 |
| Anupam Chattopadhyay | 2 | 6 | 4.23 |