Name
Title | ||
|---|---|---|
UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing. |
Abstract | ||
|---|---|---|
FPGA packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose a FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routablity. A novel physical and congestion aware packing alogrithm and several congestion aware detailed placement techniques are proposed. Compared with the top 3 winners of ISPD'16 FPGA placement contest, UTPlaceF can achieve 3.3%, 7.7% and 28.3% better routed wirelength with similar or shorter runtime. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCAD.2017.2729349 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Field programmable gate arrays,Table lookup,Routing,Digital signal processing,Random access memory,Pins | Journal | 37 |
Issue | ISSN | Citations |
4 | 0278-0070 | 11 |
PageRank | References | Authors |
0.60 | 29 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wuxi Li | 1 | 36 | 6.03 |
| Shounak Dhar | 2 | 32 | 4.84 |
| David Z. Pan | 3 | 2653 | 237.64 |