Paper Info
Title
Measure twice and cut once: Robust dynamic voltage scaling for FPGAs
Abstract
Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> depends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. This CT is used to scale V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.
Year
DOI
Venue
2016
10.1109/FPL.2016.7577342
2016 26th International Conference on Field Programmable Logic and Applications (FPL)
Keywords
Field
DocType
fast-robust-calibration,power consumption,calibration table,FPGA,dynamic voltage scaling
Dynamic voltage scaling,Large applications,Computer science,Field-programmable gate array,Real-time computing,Engineering design process,Critical path method,Temperature measurement,Calibration,Power consumption
Conference
ISSN
ISBN
Citations 
1946-1488
978-1-5090-0851-3
3
PageRank 
References 
Authors
0.42
19
4
Name
Order
Citations
PageRank
Ibrahim Ahmed1123.31
Shuze Zhao261.86
Olivier Trescases3446.99
Vaughn Betz41796134.71