Name
Abstract | ||
|---|---|---|
This paper presents a 4.4Gbps/pin all-digital LPDDR4 PHY with a bit-slice architecture in 10nm FinFET process technology. The proposed bit-slice architecture includes new I/O structure for area reduction without any off-chip performance degradation and digital duty-tuning capability to maximize the valid window margin, which contributes to low voltage operation in memory interface system. The test chip in 10nm FinFET technology demonstrated stable 4.4Gbps memory access with 112ps valid window margin (49% UI) at 690mV. The implemented 16-bit LPDDR4 PHY occupies only 0.57 mm(2) including a PLL. |
Year | Venue | Keywords |
|---|---|---|
2016 | Proceedings of the European Solid-State Circuits Conference | FinFET,LPDDR4,All-Digital DLL,Low Power,Valid Window Margin |
Field | DocType | ISSN |
Phase-locked loop,Memory interface,% area reduction,Computer science,Electronic engineering,Chip,Bandwidth (signal processing),Low voltage,PHY | Conference | 1930-8833 |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
11 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kwanyeob Chae | 1 | 38 | 5.84 |
| JongRyun Choi | 2 | 14 | 2.38 |
| Shinyoung Yi | 3 | 11 | 2.87 |
| Won Lee | 4 | 14 | 2.05 |
| Sanghoon Joo | 5 | 0 | 0.34 |
| Hyunhyuck Kim | 6 | 0 | 0.34 |
| Hyungkwon Yi | 7 | 0 | 0.34 |
| Yoonjee Nam | 8 | 0 | 1.01 |
| Jinho Choi | 9 | 0 | 0.68 |
| Sanghune Park | 10 | 1 | 3.06 |
| Sanghyun Lee | 11 | 0 | 0.34 |