Name
Abstract | ||
|---|---|---|
A 40nm CMOS line driver operating from a 5.4V supply is presented. The driver can output a 7.7V peak to peak output signal in a 50 Omega load. For high supply voltage compliance, transistor stacking and dynamic bias is being used. A line driver prototype PCB is assembled and characterized. A gain up to 19dB is measured over a 730MHz bandwidth. A OP1dB of 14dBm & P-SAT of 21.7dBm is measured in 50 Omega. During OFDM tests with a 15dB PAPR signal, a peak SNDR of 41dB is measured. |
Year | Venue | Keywords |
|---|---|---|
2016 | Proceedings of the European Solid-State Circuits Conference | CMOS,line driver,stacking,dynamic bias |
Field | DocType | ISSN |
Computer science,Voltage,Impedance matching,Electronic engineering,CMOS,Line driver,Bandwidth (signal processing),Transistor,Electrical engineering,Orthogonal frequency-division multiplexing,Stacking | Conference | 1930-8833 |
Citations | PageRank | References |
1 | 0.43 | 1 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jan Cools | 1 | 1 | 0.77 |
| Patrick Reynaert | 2 | 463 | 76.50 |