Name
Abstract | ||
|---|---|---|
In the context of system emulation, the sophistication of the emulator usually grows with the complexity of the target system model. Particularly, emulating precisely a certain CPU architecture can introduce many challenges that have to be properly explored and somehow solved to reach an accurate emulation of the target system. In this paper we present an implementation design of ARM atomic instructions for a multi-threaded version of QEMU (the Quick EMUlator), currently under development [1].To prove the correctness and performance of such an implementation, some tests have been performed showcasing a high degree of accuracy and fidelity of the emulated instructions. While this paper does not cover all possible guest architectures that QEMU supports, the described new approach results in a reliable infrastructure that eventually can address all target architectures in QEMU. |
Year | Venue | Keywords |
|---|---|---|
2016 | PROCEEDINGS - 30TH EUROPEAN CONFERENCE ON MODELLING AND SIMULATION ECMS 2016 | TCG/QEMU, atomic instructions, system emulation, instructions emulation, parallel emulator, multi-threading |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alvise Rigo | 1 | 1 | 1.03 |
| Alexander Spyridakis | 2 | 0 | 0.34 |
| D. Raho | 3 | 6 | 1.53 |