Abstract | ||
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A major shift from compute-centric to data-centric computing systems can be perceived, as novel big data workloads like cognitive computing and machine learning strongly enforce embarrassingly parallel and highly efficient processor architectures. With Moore's law having surrendered, innovative architectural concepts as well as technologies are urgently required, to enable a path for tackling exascale and beyond -- even though current computing systems face the inevitable instruction-level parallelism, power, memory, and bandwidth walls. As part of any computing system, the general perception of memories depicts unreliability, power hungriness and slowness, resulting in a future prospective bottleneck. The latter being an outcome of a pin limitation derived by packaging constraints, an unexploited tremendous row bandwidth is determinable, which off-chip diminishes to a bare minimum. Building upon a shift towards data-centric computing systems, the near-memory processing concept seems to be most promising, since power efficiency and computing performance increase by co-locating tasks on bandwidth-rich in-memory processing units, whereas data motion mitigates by the avoidance of entire memory hierarchies. By considering the umbrella of near-data processing as the urgent required breakthrough for future computing systems, this survey presents its derivations with a special emphasis on Processing-In-Memory (PIM), highlighting historical achievements in technology as well as architecture while depicting its advantages and obstacles. |
Year | DOI | Venue |
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2016 | 10.1145/2989081.2989087 | MEMSYS |
Keywords | DocType | Citations |
memory wall,bandwidth wall,processing-in-memory,near-data processing | Conference | 7 |
PageRank | References | Authors |
0.43 | 51 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Patrick Siegl | 1 | 7 | 0.43 |
Rainer Buchty | 2 | 143 | 18.44 |
Mladen Berekovic | 3 | 352 | 43.38 |