Name
Abstract | ||
|---|---|---|
ExaNest is one of three European projects that support a ground-breaking computing architecture for exascale-class systems built upon power-efficient 64-bit ARM processors. This group of projects share an "everything-close" and "share-anything" paradigm, which trims down the power consumption -- by shortening the distance of signals for most data transfers -- as well as the cost and footprint area of the installation -- by reducing the number of devices needed to meet performance targets. In ExaNeSt, we will design and implement: (i) a physical rack prototype and its liquid-cooling subsystem providing ultra-dense compute packaging, (ii) a storage architecture with distributed (in-node) non-volatile memory (NVM) devices, (iii) a unified, low-latency interconnect, designed to efficiently uphold desired Quality-of-Service guarantees for a mix of storage with inter-processor flows, and (iv) efficient rack-level memory sharing, where each page is cacheable at only a single node. Our target is to test alternative storage and interconnect options on actual hardware, using real-world HPC applications. The ExaNeSt consortium brings together technology, skills, and knowledge across the entire value chain, from computing IP, packaging, and system deployment, all the way up to operating systems, storage, HPC, big data frameworks, and cutting-edge applications. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/DSD.2016.106 | 2016 Euromicro Conference on Digital System Design (DSD) |
Keywords | Field | DocType |
ExaNeSt project,exascale system interconnects,exascale systems storage,exascale systems packaging,European project,computing architecture,exascale-class systems,power-efficient 64-bit ARM processors,everything-close paradigm,share-anything paradigm,power consumption trimming,signals distance shortening,data transfers,physical rack prototype,liquid-cooling subsystem,ultra-dense compute packaging,storage architecture,distributed non-volatile memory devices,in-node NVM devices,unified interconnect,low-latency interconnect,quality-of-service guarantees,inter-processor flows,rack-level memory sharing,page caching,alternative storage,HPC applications,ExaNeSt consortium | ARM architecture,Architecture,Rack,System deployment,Computer science,Parallel computing,Real-time computing,Footprint,Interconnection,Big data,Embedded system,Power consumption | Conference |
ISBN | Citations | PageRank |
978-1-5090-2818-4 | 8 | 0.54 |
References | Authors | |
16 | 27 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manolis Katevenis | 1 | 378 | 36.21 |
| Nikolaos Chrysos | 2 | 60 | 8.56 |
| Manolis Marazakis | 3 | 136 | 20.29 |
| Iakovos Mavroidis | 4 | 31 | 6.30 |
| Fabien Chaix | 5 | 11 | 0.93 |
| N. Kallimanis | 6 | 8 | 0.54 |
| Javier Navaridas | 7 | 8 | 0.54 |
| John Goodacre | 8 | 46 | 7.35 |
| Piero Vicini | 9 | 135 | 20.26 |
| Andrea Biagioni | 10 | 83 | 14.81 |
| Pier Stanislao Paolucci | 11 | 140 | 23.56 |
| Alessandro Lonardo | 12 | 101 | 17.81 |
| Elena Pastorelli | 13 | 35 | 8.34 |
| Francesca Lo Cicero | 14 | 90 | 15.81 |
| Roberto Ammendola | 15 | 84 | 14.53 |
| P. Hopton | 16 | 8 | 0.54 |
| P. Coates | 17 | 8 | 0.54 |
| G. Taffoni | 18 | 8 | 0.54 |
| S. Cozzini | 19 | 8 | 0.54 |
| M. Kersten | 20 | 8 | 0.54 |
| Y. Zhang | 21 | 8 | 0.88 |
| Julio Sahuquillo | 22 | 420 | 53.71 |
| Sergio Lechago | 23 | 8 | 0.54 |
| C. Pinto | 24 | 8 | 0.54 |
| B. Lietzow | 25 | 8 | 0.54 |
| D. Everett | 26 | 8 | 0.54 |
| G. Perna | 27 | 8 | 0.54 |