Name
Abstract | ||
|---|---|---|
The non-uniform distributed traffic of chip multi-processor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. At low loads, this router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications' execution time by 16.9% in average compared to low-latency router SWIFT. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/DSD.2016.40 | 2016 Euromicro Conference on Digital System Design (DSD) |
Keywords | Field | DocType |
adaptive,NoC,low-latency,router | Computer science,Parallel computing,Bridge router,Computer network,Real-time computing,Link state packet,Core router,P Router,Router,Latency (engineering),One-armed router,Metrics | Conference |
ISBN | Citations | PageRank |
978-1-5090-2818-4 | 1 | 0.35 |
References | Authors | |
17 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen Zong | 1 | 11 | 2.55 |
| Liang Wang | 2 | 1567 | 158.46 |
| Qiang Xu | 3 | 2165 | 135.87 |
| Michael Opoku Agyeman | 4 | 71 | 12.80 |