Paper Info
Title
A Majority-Based Reliability-Aware Task-Mapping in High-Performance Homogenous NoC Architectures
Abstract
This paper presents a new reliability-aware task mapping approach in a many-core platform at design time for applications with DAG-based task graphs. The main goal of this approach is to devise a task mapping scenario which meets the predefined reliability threshold ensuring minimum performance degradation. The proposed approach uses majority-voting replication technique to fulfill error-masking capability. A quantitative reliability model is also proposed for the platform. Our platform is a homogenous many-core architecture with mesh-based interconnection using traditional deterministic XY routing algorithm. The novel 3-step iterative approach is applicable to an unlimited number of fault types. All parts of the platform including cores, links and routers are assumed to be prone to failures. We used the MNLP optimization technique to find the optimal mapping of presented task graph. Experimental results show that our suggested task mapping approach not only comply with the predefined reliability threshold but also notable time complexity reduction is achieved with respect to exhaustive space exploration.
Year
DOI
Venue
2016
10.1109/DSD.2016.28
2016 Euromicro Conference on Digital System Design (DSD)
Keywords
Field
DocType
Reliability,Performance,Task Mapping,Many core,Network-on-Chip
Graph,Architecture,Computer science,Task mapping,Network on a chip,Real-time computing,Space exploration,Time complexity,Interconnection,Reliability model,Distributed computing
Conference
ISBN
Citations 
PageRank 
978-1-5090-2818-4
2
0.38
References 
Authors
15
4
Name
Order
Citations
PageRank
Alireza Namazi1163.36
Meisam Abdollahi2386.34
Saeed Safari314324.94
Siamak Mohammadi4278.23